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Networks on Chip

Edited by Axel Jantsch, Edited by Hannu Tenhunen

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normal price: R 7 379.95

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As the number of processor cores and IP blocks integrated on a single chip is steadily growing, a systematic approach to design the communication infrastructure becomes necessary. Different variants of packed switched on-chip networks have been proposed by several groups during the past two years. This book summarizes the state of the art of these efforts and discusses the major issues from the physical integration to architecture to operating systems and application interfaces. It also provides a guideline and vision about the direction this field is moving to. Moreover, the book outlines the consequences of adopting design platforms based on packet switched network. The consequences may in fact be far reaching because many of the topics of distributed systems, distributed real-time systems, fault tolerant systems, parallel computer architecture, parallel programming as well as traditional system-on-chip issues will appear relevant but within the constraints of a single chip VLSI implementation.

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Normally shipped | Available from overseas. Usually dispatched in 14 days
Publisher | Springer-Verlag New York Inc.
Published date | 5 Nov 2010
Language |
Format | Paperback / softback
Pages | 303
Dimensions | 235 x 155 x 0mm (L x W x H)
Weight | 0g
ISBN | 978-1-4419-5344-5
Readership Age |
BISAC | computers / computer architecture


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